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Annals of Computer Science and Information Systems, Volume 18

Proceedings of the 2019 Federated Conference on Computer Science and Information Systems

The Low-Area FPGA Design for the Post-Quantum Cryptography Proposal Round5

DOI: http://dx.doi.org/10.15439/2019F230

Citation: Proceedings of the 2019 Federated Conference on Computer Science and Information Systems, M. Ganzha, L. Maciaszek, M. Paprzycki (eds). ACSIS, Vol. 18, pages 213–219 ()

Full text

Abstract. Post-Quantum Cryptography (PQC) is getting attention recently. The main reason of this situation is the announcement by the U.S. National Institute for Standard and Technology (NIST) about an opening of the standardization process for PQC. Recently NIST published a list of submissions qualified to the second round of this process. One of the selected algorithms is Round5, offering a key encapsulation mechanism (KEM) and public key encryption (PKE). Due to high complexity of post-quantum cryptosystems, only a few FPGA implementations have been reported to date. In this paper, we report results for low-area purely-hardware implementation of Round5 targeting low-cost FPGAs.

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